1. Field of the Invention
The present invention relates to a semiconductor device containing an insulating gate type transistor and to a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a semiconductor device containing an insulating gate type transistor such as a MOS transistor has been manufactured with a method in which a transistor for high voltage and a transistor for low voltage (high speed) are formed simultaneously on one chip (wafer). That is, in order to reduce the number of steps as many as possible, the insulating gate type transistor comprising a high voltage part and a low voltage part has been formed with a fewer steps.
However, it has been very difficult to realize the high voltage part and low voltage part at such a level that a high breakdown voltage characteristic of the high voltage part and a high speed characteristic of both parts are satisfied simultaneously while maintaining a small number of steps.
It has been a conventional practice that the high and low voltage parts are made in different steps. For instance, a gate insulting film for high voltage and that for low voltage are formed in different steps, and the step of an LDD implantation (a first impurity implantation for forming a region that becomes an LDD region) is performed separately in the high voltage part and low voltage part.
FIGS. 24 to 28 are sectional views illustrating a sequence of steps in a conventional method of manufacturing a semiconductor device containing a transistor for high voltage and a transistor for low voltage. The conventional method will be described by referring to these figures.
Referring to FIG. 24, an insulating film 2 having a relatively large thickness is formed on a semiconductor substrate 1 such as a silicon substrate.
Referring to FIG. 25, a patterned resist 3 is formed so as to cover the surface of a high voltage operation region A1. By using the resist 3 as a mask, an etching process to the insulating film 2 is performed to remove the insulating film 2 formed on the surface of a low voltage operation region A2.
Referring to FIG. 26, the resist 3 is then removed and an insulating film having a relatively small thickness is formed on the entire surface. Thereby, an insulating film 4 is formed in the low voltage operation region A2 and the thickness of the insulating film 2 in the high voltage operation region A1 is slightly increased. Subsequently, a conductive layer 5 is deposited on the entire surface.
Referring to FIG. 27, the conductive layer 5 is selectively etched so that a gate insulating film 61 and a gate electrode 62 are formed in the high voltage operation region A1, and a gate insulating film 71 and a gate electrode 72 are formed in the low voltage operation region A2 at the same time. In this case, the gate insulating film 61 is formed so as to have a larger thickness than the gate insulating film 71, and the gate electrode 62 is formed so as to have a longer gate length than the gate electrode 72.
Subsequently, a first LDD implantation process for forming an impurity diffusion region 63 that becomes an LDD region is performed by implanting an impurity ion 64 only to the high voltage operation region A1, while the low voltage operation region A2 is covered with a first resist (not shown in FIG. 27). A second LDD implantation process for forming an impurity diffusion region 73 that becomes an LDD region is performed by implanting an impurity ion 74 only to the low voltage operation region A2, while the high voltage operation region A1 is covered with a second resist (not shown in FIG. 27).
Thus, the first and second LDD implantations are performed in different steps, and the impurity diffusion region 63 is usually formed so as to be deeper than the impurity diffusion region 73.
Referring to FIG. 28, an insulating layer (sidewall film) that becomes a lower layer sidewall or an upper layer sidewall is formed successively, followed by etch back. Thereby, in the high voltage operation region A1, a sidewall made up of an upper layer sidewall 65 and a lower layer sidewall 66 is formed on the side surface of the gate electrode 62. A1so, in the low voltage operation region A2, a sidewall made up of an upper layer sidewall 75 and a lower layer sidewall 76 is formed on the side surface of the gate electrode 72.
Subsequently, in the high and low voltage operation regions A1 and A2, a source/drain region forming process is performed by implanting an impurity ion 55 from above, respectively. In this implantation, the gate electrode 62, upper layer sidewall 65 and lower layer sidewall 66 are used as a mask in the high voltage operation region A1, and the gate electrode 72, upper layer sidewall 75 and lower layer sidewall 76 are used as a mask in the low voltage operation region A2. Thereby, a source/drain region 67 and an LDD region 68 (an impurity diffusion region 63 underlying the sidewalls 65 and 66) are formed in the high voltage operation region A1, and a source/drain region 77 and an LDD region 78 (an impurity diffusion region 73 underlying the sidewalls 75 and 76) are formed in the low voltage operation region A2. Note that the LDD region is also called xe2x80x9cextension region.xe2x80x9d
As a result, a MOS transistor Q11 for high voltage made up of the gate insulating film 61, gate electrode 62, upper layer sidewall 65, lower layer sidewall 66, source/drain region 67 and LDD region 68 is formed in the high voltage operation region A1, and a MOS transistor Q12 for low voltage made up of the gate insulating film 71, gate electrode 72, upper layer sidewall 75, lower layer sidewall 76, source/drain region 77 and LDD region 78 is formed in the low voltage operation region A2. As used herein, the term xe2x80x9cMOS transistor for high voltagexe2x80x9d means mainly a MOS transistor for input-output that operates at approximately 3.3 V, and the term xe2x80x9cMOS transistor for low voltagexe2x80x9d means mainly a MOS transistor for logic operation that operates at approximately 1.8 V.
FIG. 29 is a flowchart illustrating a procedure in the case when a semiconductor device of a CMOS structure is obtained by the conventional method as above described. The flowchart of FIG. 29 illustrates a sequence of steps taken after forming a gate insulating film and a gate electrode in each of high and low voltage operation regions A1 and A2.
In step S1, an LDD implantation process to a NMOS transistor for low voltage is performed. In step S2, an LDD implantation process to a PMOS transistor for low voltage is performed. In step S3, an LDD implantation process to a NMOS transistor for high voltage is performed. In step S4, an LDD implantation process to a PMOS transistor for high voltage is performed.
The order of steps S1 to S4 is changeable. A pocket implantation process for forming a pocket region may be added in steps S1 and S2, respectively.
In step S5, a pre-treatment using a wet process (including a wet etching and cleaning with a liquid) is performed. Example of the pre-treatment using the wet process is RCA cleaning. The term xe2x80x9cRCA cleaningxe2x80x9d means a process which comprises a treatment with NH4OH/H2O2 (a process of removing particles) and a treatment with HCl/H2O2 (a process of removing metal contamination).
In step S6, a lower layer sidewall film is formed. In step S7, an upper layer sidewall film is formed, followed by a post-treatment, such as an etch back and a treatment with HF (hydrofluoric acid), so that a sidewall is formed on the side surface of the gate electrode of all MOS transistors.
In step S8, a source/drain region forming process is performed to all NMOS transistors (for high voltage and for low voltage). In step S9, a source/drain region forming process is performed to all PMOS transistors. The order of steps S8 and S9 is changeable.
Subsequently, silicide (salicide) such as CoSi2 or TiSi2 is formed on the surface of the source/drain regions and on the surface of the gate electrodes to complete all the MOS transistors.
With the conventional manufacturing method as described, the MOS transistor for high voltage and the MOS transistor for low voltage can be formed on one chip with a relatively few steps.
Between a MOS transistor Q11 for high voltage and a MOS transistor Q12 for low voltage in FIG. 28, there are three differences that the gate insulating film 61 has a larger thickness than the gate insulating film 71; the gate electrode 62 has a larger gate length than the gate electrode 72; and the LDD region 68 is formed so as to be deeper than the LDD region 78.
That is, the MOS transistor for high voltage differs from the MOS transistor for low voltage in three points that the gate insulating film for high voltage has a larger thickness than the gate insulating film for low voltage; that the gate electrode for high voltage has a larger gate length than the gate electrode for low voltage; and that the LDD region for high voltage is formed so as to be deeper than the LDD region for low voltage.
However, these three differences lead to a low freedom of design and it is thus difficult to optimize the operation characteristics of both the MOS transistor for high voltage and the MOS transistor for low voltage.
According to a first aspect of the invention, a semiconductor device containing first and second transistors of an insulating gate type formed in a semiconductor substrate, each of the first and second transistors comprising: a gate insulating film selectively disposed on the semiconductor substrate, the surface of the semiconductor substrate underlying the gate insulating film being defined as a channel region; a gate electrode disposed on the gate insulating film; a sidewall disposed adjacent to the side surface of the gate electrode; and a source/drain region disposed in the surface of the semiconductor substrate with the channel region interposed therebetween, is characterized in that the sidewall of the first transistor has a smaller forming width and a smaller forming height than the sidewall of the second transistor.
According to a second aspect of the invention, in the semiconductor device of the first aspect, the sidewalls of the first and second transistors have a lower layer sidewall disposed on the side surface of the gate electrode and on the surface of the semiconductor substrate, and have an upper layer sidewall disposed on the lower layer sidewall, a film thickness of the lower layer sidewall of the sidewall of the first transistor is smaller than a film thickness of the lower layer sidewall of the second transistor.
According to a third aspect of the invention, the semiconductor device of the second aspect is characterized in: that a recessed amount of the end portion of the lower layer sidewall from the end portion of the upper layer sidewall toward the gate electrode in the first transistor is larger than a recessed amount of the end portion of the lower layer sidewall from the end portion of the upper layer sidewall toward the gate electrode in the second transistor; and that a forming length of the source/drain region from the end portion of the sidewall to the gate electrode in the first transistor is larger than a forming length of the source/drain region from the end portion of the sidewall to the gate electrode in the second transistor.
According to a fourth aspect of the invention, the semiconductor device of the second aspect is characterized in: that the film thickness of the lower layer sidewall of the first transistor includes a first film thickness in the area adjacent to the side surface of the gate electrode and a second film thickness in the area on the surface of the semiconductor substrate; and that the first film thickness is smaller than the second film thickness or reduces to zero.
According to a fifth aspect of the invention, the semiconductor device of the first aspect is characterized in: that the sidewall wall of the second transistor has a lower layer sidewall disposed on the side surface of the gate electrode and on the surface of the semiconductor substrate, and has an upper layer sidewall disposed on the lower layer sidewall; and that the sidewall of the first transistor includes a sidewall, the shape of which is substantially the same as the upper layer sidewall of the second transistor.
According to a sixth aspect of the invention, the semiconductor device of the fifth aspect is characterized in that the sidewall of the first transistor has a thermal oxide film in its undermost layer.
According to a seventh aspect of the invention, the semiconductor device of the first aspect is characterized in that the semiconductor substrate includes a SOI substrate comprising a substrate, at least the surface of which is insulative, and a semiconductor layer disposed on the surface of the substrate.
According to an eighth aspect of the invention, the semiconductor device of the first aspect is characterized in that the conductivity type of the first and second transistors includes an N type.
According to a ninth aspect of the invention, the semiconductor device of the first aspect is characterized in that the conductivity type of the first and second transistors includes a P type.
According to a tenth aspect, a method of manufacturing a semiconductor device containing first and second transistors of an insulating gate type formed in a semiconductor substrate, comprises the steps of: (a) forming first and second gate insulating films in first and second regions on the semiconductor substrate, respectively, the surface of the semiconductor substrate under the first and second gate insulating films being defined as first and second channel regions, respectively; (b) forming first and second gate electrodes on the first and second gate insulating films, respectively; (c) forming a second impurity diffusion region by introducing impurity only to the second region by using the second gate electrode as a mask; (d) forming a lower layer sidewall film on the entire surface; (e) forming a first impurity diffusion region by introducing impurity only to the first region over the lower layer sidewall film by using the first gate electrode as a mask; (f) forming an upper layer sidewall film on the entire surface; (g) performing an etch back process to the upper layer sidewall film so that on the side surfaces of the first and second gate electrodes, first and second upper layer sidewalls are formed with the lower layer sidewall film interposed therebetween; (h) selectively removing the lower layer sidewall film to form first and second lower layer sidewalls on the side surfaces of the first and second gate electrodes and on the surface of the semiconductor substrate beneath the first and second upper layer sidewalls; and (i) forming a first source/drain region by introducing impurity by using the first upper layer and lower layer sidewalls and the first gate electrode as a mask, and forming a second source/drain region by introducing impurity by using the second upper layer and lower layer sidewalls and the second gate electrode as a mask, the first impurity diffusion region adjacent to the first source/drain region in the direction of the first gate electrode being defined as a first LDD region, the second impurity diffusion region adjacent to the second source/drain region in the direction of the second gate electrode being defined as a second LDD region, wherein the first transistor comprises the first gate insulating film, the first gate electrode, the first upper layer sidewall, the first lower layer sidewall, the first source/drain region and the first LDD region, and the second transistor comprises the second gate insulating film, the second gate electrode, the second upper layer sidewall, the second lower layer sidewall, the second source/drain region and the second LDD region.
According to an eleventh aspect of the invention, the method of the tenth aspect is characterized in: that the first transistor includes a NMOS transistor for high voltage; and that the second transistor includes a NMOS transistor for low voltage, a PMOS transistor for low voltage and a PMOS transistor for high voltage.
According to a twelfth aspect of the invention, the method of the tenth aspect is characterized in: the first transistor includes a NMOS transistor for high voltage and a PMOS transistor for high voltage; and that the second transistor includes a NMOS transistor for low voltage and a PMOS transistor for low voltage.
According to a thirteenth aspect of the invention, the method of the tenth aspect is characterized in: the first transistor includes a NMOS transistor for high voltage and a PMOS transistor for low voltage; and that the second transistor includes an NMOS transistor for low voltage and a PMOS transistor for high voltage.
According to a fourteenth aspect of the invention, the method of the tenth aspect is characterized in: that the first transistor includes a NMOS transistor for high voltage, a PMOS transistor for high voltage and a PMOS transistor for low voltage; and that the second transistor includes a NMOS transistor for low voltage.
According to a fifteenth aspect of the invention, the method of the tenth aspect further comprises the step of: (j) performing, before the step (d), a RTA (rapid thermal annealing) process.
According to a sixteenth aspect of the invention, the method of the tenth aspect is characterized in that the step (d) includes the step of forming the lower layer sidewall film by using TEOS as a material.
According to a seventeenth aspect of the invention, the method of the tenth aspect is characterized in the step (d) includes the step of forming the lower layer sidewall film by using a high temperature CVD thermal film as a material.
According to an eighteenth aspect of the invention, the method of the tenth aspect further comprises the step of: (k) performing, between the steps (e) and (f), a pre-treatment with a wet process.
According to a nineteenth aspect of the invention, the method of the eighteenth aspect is characterized in that the step (h) includes the step of removing the lower layer sidewall film by a wet etching.
According to a twentieth aspect of the invention, the method of the tenth aspect is characterized in that the step (e) includes the step of introducing nitrogen into the first impurity diffusion region.
In the semiconductor device of the first aspect, the sidewall of the first transistor is formed so as to have a smaller forming width and a smaller forming height than the sidewall of the second transistor. This enables to obtain the first transistor having a high driving capability than the second transistor, and the second transistor having a low parasitic capacity than the first transistor.
Therefore, the use of the first transistor for high voltage operation and the use of the second transistor for low voltage operation enable to provide a semiconductor device that optimizes the operation characteristics of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage.
In the semiconductor device of the second aspect, between the sidewalls of the first and second transistors, the forming width and forming height can be changed relatively easily by reducing the thickness of the lower layer sidewall of the sidewall of the first transistor than the thickness of the lower layer sidewall of the sidewall of the second transistor.
With the semiconductor device structure of the third aspect, a further improvement in driving capability of the first transistor is attainable by reducing the effective channel length of the channel region.
In the semiconductor device of the fourth aspect, the driving capability of the first transistor can be increased because the influence of field formed by the gate electrode of the first transistor can be given strongly to the source/drain region underlying the sidewall, by making the first film thickness smaller than the second film thickness to further reduce the forming width of the sidewall of the first transistor.
In the semiconductor device of the fifth aspect, the driving capability of the first transistor can be increased because the influence of field formed by the gate electrode of the first transistor can be given strongly to the source/drain region underlying the sidewall, by arranging so that the forming width of the sidewall of the first transistor is narrower than the forming width of the second sidewall by the amount of the lower layer sidewall.
In the semiconductor device of the sixth aspect, the driving capability of the first transistor can be increased because the influence of field formed by the gate electrode of the first transistor can be given strongly to the source/drain region underlying the sidewall, by arranging so that the forming width of the sidewall of the first transistor is narrower than the forming width of the second sidewall by the amount of absence of a lower layer sidewall in the direction of the forming width.
With the seventh aspect, a semiconductor device that optimizes the operation characteristics of both an insulating gate type transistor for high voltage and an insulting gate type transistor for low voltage can be obtained even on a SOI substrate.
With the semiconductor device of the eighth aspect, it is able to use the first or second transistor as the occasion demands in an insulating gate type transistor of which conductivity type is N type.
With the semiconductor device of the ninth aspect, it is able to use the first or second transistor as the occasion demands in an insulating gate type transistor of which conductivity type is P type.
With the method of the tenth aspect, the resistance to hot carrier of the first transistor can be increased by the amount that the formation of a trap state on the semiconductor substrate surface is suppressed, because in the step (e) the first impurity diffusion region is formed only in the first region by introducing impurity over the lower layer sidewall film by using the first gate electrode as a mask.
In addition, since the impurity is introduced over the lower layer sidewall film, at the same implantation energy, the first impurity diffusion region to be an LDD region can be formed so as to be relatively shallow, as compared to the case of directly introducing impurity. It is therefore able to obtain a good short channel characteristic whereby it is unsusceptible to short channel effect.
With the method of the tenth aspect, the number of steps can be minimized because the steps other than the steps (e) and (c) for forming the first and second impurity diffusion regions are commonly executable between the first and second transistors.
With the method of the eleventh aspect, it is able to obtain a NMOS transistor for high voltage with an improved resistance to hot carrier.
With the method of the twelfth aspect, it is able to obtain NMOS and PMOS transistors for high voltage with an improved resistance to hot carrier.
With the method of the thirteenth aspect, it is able to obtain a NMOS transistor for high voltage with an improved resistance to hot carrier, and a PMOS transistor for low voltage with an improved short channel characteristic.
With the method of the fourteenth aspect, it is able to obtain NMOS and PMOS transistors for high voltage with an improved resistance to hot carrier, and a PMOS transistor for low voltage with an improved short channel characteristic.
With the method of the fifteenth aspect, TED (transient enhanced diffusion) phenomenon that occurs in the step (d) can be suppressed effectively by performing a RTA process in the step (j) before the step (d) for forming the lower layer sidewall film.
With the method of the sixteenth aspect, the trap state at the interface between the lower layer sidewall film and the semiconductor substrate can be further reduced by that in the step (d) the lower layer sidewall film is formed by using TEOS as a material.
With the method of the seventeenth aspect, the trap state at the interface between the lower layer sidewall film and the semiconductor substrate can be further reduced by that in the step (d) the lower layer sidewall film is formed by using a high temperature thermal CVD oxide film as a material.
With the method of the eighteenth aspect, the first region has a smaller film thickness than the second region in the lower layer sidewall film because the film thickness of the first region of the lower layer sidewall film into which the impurity is introduced in the step (e), is reduced due to the pretreatment with a wet process in the step (k).
As a result, the sidewall of the first transistor (the first upper and lower layer sidewalls) has a smaller forming width and a smaller forming height than the sidewall of the second transistor (the second upper and lower layer sidewalls). Therefore, the first transistor has a higher driving capability than the second transistor, and the second transistor has a lower parasitic capacity than the first transistor.
With the method of the nineteenth aspect, the lower layer sidewall film can be etched in the area extending from the end portion of the first and second upper layer sidewalls to the first and second gate electrodes, respectively, because in the step (h) the lower sidewall film is removed by a wet etching.
Therefore, by utilizing the fact that the film thickness of the first region is smaller than that of the second region in the lower layer sidewall film, the recessed amount of the end portion of the first lower layer sidewall from the end portion of the first upper layer sidewall toward the first gate electrode can be increased than the recessed amount of the end portion of the second lower layer sidewall from the end portion of the second upper layer sidewall toward the second gate electrode.
As a result, in the first and second source/drain regions formed in the step (i), the forming length from the end portion of the first sidewall of the first source/drain region to the first gate electrode is larger than the forming length of the second source/drain region from the end portion of the second sidewall to the second gate electrode. Therefore, the first transistor with a further improved driving capability can be obtained by further reducing the effective channel length of the channel region.
With the method of the twentieth aspect, the trap state at the interface with the semiconductor substrate beneath the lower layer sidewall can be further reduced by introducing nitrogen into the first impurity diffusion region in the step (e).
It is an object of the present invention to overcome the foregoing drawbacks by providing a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, as well as a method of manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.